Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Another type of PLD is the Complex Programmable Logic Device (“CPLD”). A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
Heretofore, performance of a design instantiated in programmable logic of an FPGA (“FPGA fabric”) was done for FPGAs fabricated in a single Fab (fabrication facility). Accordingly, because each device was manufactured in the same Fab, such devices generally had equivalent performance levels, subject to variation within the semiconductor processing of the single-Fab environment. For example, devices manufactured within a single Fab had different maximum operating frequencies and thus were binned into bins according to these differences (“speed binning”).
For each speed bin, speed files for each particular type of FPGA were generated. These speed files were created with worst-case delays for each type of part of an FPGA for a particular speed bin. Timing analysis for an FPGA, in contrast to timing analysis for an application-specific integrated circuit (“ASIC”), is less deterministic as a circuit design instantiated in programmable logic may significantly vary from user to user. Thus, since each user may have a different design, it is more difficult to know whether timing constraints of a design may be met after instantiation in an FPGA, in contrast to fabrication of such design as an ASIC.
For an FPGA, delays associated with sub-circuits are characterized. Because such sub-circuits may be repeated, possibly for thousands of instances in each FPGA, the same delay may be characterized once for each instance of a sub-circuit of an FPGA. Examples of different classes of delay include routing delay, Look Up Table (“LUT”) delay, and flip-flop clock-to-out delay, among other well-known classifications of sub-circuit delays.
In a single Fab environment, a speed file created for an FPGA would define the worst-case performance delays of sub-circuits of such FPGA. The speed file may then be used to assist compilation of a user's circuit design for instantiation into the FPGA fabric. Thus, a user may verify that performance requirements, including timing constraints, could be met by instantiation of such circuit design into a target FPGA platform.
However, multiple Fabs, which may be multiple foundries, may be used to manufacture FPGAs. Variation in semiconductor processing among these Fabs promotes different delay values for same sub-circuits of a same FPGA part type.
Accordingly, it would be both desirable and useful to provide means for performance characterization of integrated circuits having programmable logic manufactured in a multi-Fab environment.